VLSI Digital Design using VHDL and Hardware:Handson

Learning Outcome 1

After the course students with little or no VHDL knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations. and  Gain a strong foundation in VHDL RTL and test bench coding techniques.  Write VHDL RTL hardware designs using good coding practices.  Learn the synthesizable subset of VHDL.  Use types, overloading, and conversion functions from standard VHDL packages (std_logic_1164).  Distinguish coding for synthesis versus coding for simulation.  Know about VHDL constructs used in simulation and synthesis environments.  Write VHDL Bench s for simulation.  Target and optimize Xilinx FPGAs by using VHDL.  Run a timing simulation by using Xilinx ISim libraries.  Create and manage designs within the Xilinx Design Suite.  Correctly model combinational and sequential hardware blocks.  Write User constraints files for any FPGA board.